The invention relates to a circuit arrangement for limiting the transmission speed of binary data signals, wherein a first input is supplied with the data signals and a second input is supplied with associated element pulse trains, which have a fixed pulse duration when their repetition frequency is equal to a given limit frequency. The binary output signals corresponding to the data signals are emitted at an output when the repetition frequency of the element pulse trains does not exceed a given limit frequency.
In the pulsed transmission of data, the transmission speed of the data signals is determined by the repetition of the element pulse train belonging to the data signals. If the repetition frequency of the element pulse train is not limited, a circuit arrangement is required which blocks the emission of data signals when the repetition frequency of the element pulse trains exceeds a given limit frequency.
German Auselgeschrift No. 1,804,719 discloses a circuit arrangement for the monitoring of data signals. With the aid of this circuit arrangement, the form of the data signals is compared with a form determined by a tolerance plan, and those data signals are recognized as being faulty which exceed the inner or outer limit of the tolerance plan. However, this circuit arrangement is not suitable for limiting the transmission speed of data signals, because it recognizes as faulty all data signals whose transmission speed is greater than or lower than a transmission speed established by the tolerance plan.
A circuit arrangement has previously been proposed for limiting transmission speed of data signals. In this circuit arrangement the element duration of the data signals is compared with a theoretical element duration. Data signals whose element duration is shorter than the theoretical element duration are, in this circuit arrangement, lengthened to the theoretical element duration. Thus, this circuit arrangement emits signals even when the transmission speed of the data signals exceeds a transmission speed assigned to the theoretical element duration at its input. Also, the circuit arrangement is provided for data signals which are transmitted in a nonpulsed fashion.
An object of the invention is to provide a circuit arrangement for limiting the transmission speed of binary data signals capable of blocking data signals in case the repetition frequency of the associated element pulse train exceeds a given limit frequency.